A Cache is the most basic and important component in a modern computer memory system. A main function of the Cache is to moderate a difference of performance between a high-speed processor and a low-speed external memory, thereby preventing performance of the processor from being affected because of waiting for memory data.
For reading, writing, or storing in a Cache, there are two cases: hit and miss. If data that needs to be read and written exists in the Cache, it indicates hit, and in this case, speed of reading and writing in the Cache is relatively high; otherwise, it indicates miss, and in this case, a corresponding data block needs to be loaded from an external memory.
A basic design idea for a modern Cache controller is as follows: An upper-layer command interface issues a read/write command, and the Cache controller first checks whether data corresponding to an address of the command is buffered in a Cache memory. If a hit occurs, an read/write operation is completed directly in the Cache memory; if a miss occurs, the command needs to be blocked temporarily, a read command needs to be initiated to an external memory, then data read from the external memory needs to be written into the Cache memory, and the previously blocked upper-layer command needs to be invoked again, thereby completing read/write of the data.
However, if this technology is adopted, in a case that an operation command misses a Cache memory in a Cache controller, the number of times of arbitration applications and the number of times of read and write are relatively high for the Cache memory, which causes a problem that a delay in an operation on the Cache memory and a bandwidth occupied by the operation are relatively high.